By Ibrahim (Abe) M. Elfadel, Gerhard Fettweis
This ebook explains for readers how 3D chip stacks promise to extend the extent of on-chip integration, and to layout new heterogeneous semiconductor units that mix chips of other integration applied sciences (incl. sensors) in one package deal of the smallest attainable dimension. The authors specialize in heterogeneous 3D integration, addressing probably the most vital demanding situations during this rising know-how, together with contactless, optics-based, and carbon-nanotube-based 3D integration, in addition to signal-integrity and thermal administration matters in copper-based 3D integration. insurance additionally comprises the 3D heterogeneous integration of energy resources, photonic units, and non-volatile thoughts in keeping with new fabrics systems.
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Extra info for 3D Stacked Chips: From Emerging Processes to Heterogeneous Systems
Front and back side lithography is used to generate the metallization layer mask for the subsequent patterning processes. The copper layer is structured in a wet etching process and the redistribution lines on the front and back side of the wafer are created by pattern plating. The seed and the barrier layers are removed afterwards in a plasma etch process. In a waferbumping process, SnAg or PbSn solder bumps are fabricated by electrochemical deposition (ECD) and reflow. The properties of different stop layers are investigated in Sect.
In contrast to the PE-CVD of TEOS, the deposition rate in thermal oxidation does not depend on the aspect ratio and the layer thickness of the insulator is constant on the whole wafer. For thermal oxidation an oxidizing agent diffuses to the SiO2 /Si interface at high temperature and reacts with the Si substrate. Thermal oxidation of silicon is usually performed at a temperature between 800 and 1200 ı C. Thermal oxide is based on a chemical reaction of oxygen and silicon, and requires the diffusion of the oxidant through the already grown SiO2 to the unreacted Si surface.
IEEE Trans. Very Large Scale Integr. Syst. 15(10), 1081–1090 (2007) Chapter 2 Copper-Based TSV: Interposer Sebastian Killge, Volker Neumann, and Johann W. 1 Introduction Through-silicon via (TSV) fabrication consists mainly of the following steps: etching, deposition of insulator, deposition of barrier and seed layers, and electrochemical plating. Depending on the application, the TSV structures differ in size, aspect ratio, density, materials, and technology. Each application has its own requirements which affect the whole processing scheme.
3D Stacked Chips: From Emerging Processes to Heterogeneous Systems by Ibrahim (Abe) M. Elfadel, Gerhard Fettweis